A charge pump is a circuit which uses capacitors and switches to store and transfer charge to convert a given DC voltage into a different DC voltage. Charge pumps can double, invert or generate arbitrary voltages, depending on the controller and circuit topology. They are capable of high efficiencies, sometimes as high as 90-95%.
An existing charge pump architecture is shown in FIG. 1. This is one example of a charge pump and is not intended to limit the field to which this invention relates. The charge pump in FIG. 1 comprises a main charge pump 10 and, optionally, an auxiliary pump 12 which may be required in some cases to generate voltages which are high enough to drive the gates of the main pump's switching circuit or means, which in a preferred embodiment comprise MOSFETs. However, it is to be understood that any other appropriate transistor or other switching circuit could be used as required.
The switch means are operable to alternately store charge onto first and second flying capacitors Cf1 and Cf2 by their selective connection to a first voltage source 14, connect the flying capacitors to a pedestal voltage source 16 and alternately discharging the flying capacitors Cf1 and Cf2 to a reservoir capacitor Crsvr for use in driving a load 18. The load 18 can be of any of a variety of different types, such as a resistive load or a current source for example. It is to be appreciated that the first voltage source 14 and pedestal voltage source 16 can be provided by a single potential difference. Maintaining them as separate voltage sources also gives greater flexibility in controlling the amount of charge to be injected during the pumping action. The present invention applies equally to either case, that is, whether the first voltage source 14 and pedestal voltage source 16 are combined or separate. When separate, the two voltage sources may be of equal or different values, as required.
The switch means comprise a first pedestal switch means SPL1 which selectively connects the first flying capacitor Cf1 either to the pedestal voltage source 16 or to ground, having a high state where the first flying capacitor Cf1 is connected to the pedestal voltage source 16 and a low state where the first flying capacitor Cf1 is both connected to ground and isolated from the pedestal voltage source 16.
The switch means also comprise a first charge switch means SCH1, operable between a high state which connects the first flying capacitor Cf1 to the first voltage source 14, when the other terminal of capacitor Cf1 is connected to ground by switch means SPL1, to charge the first flying capacitor Cf1, and a low state where the first flying capacitor Cf1 is isolated from the first voltage source 14. A first discharge switch means SDCH1 is operable between a high state where the first flying capacitor Cf1 and the reservoir capacitor Crsvr are disconnected, and a low state wherein the first flying capacitor Cf1 and the reservoir capacitor Crsvr are connected, when the other terminal of capacitor Cf1 is connected to the pedestal voltage source 16, so that charge is transferred from the first flying capacitor Cf1 to the reservoir capacitor Crsvr.
In a similar fashion, there is provided a second pedestal switch means SPL2 which selectively connects the second flying capacitor Cf2 either to the pedestal voltage source 16 or to ground, having a high state where the second flying capacitor Cf2 is connected to the pedestal voltage source 16 and a low state where the second flying capacitor Cf2 is both connected to ground and isolated from the pedestal voltage source 16. Also provided is a second charge switch means SCH2, operable between a high state which connects the second flying capacitor Cf2 to the first voltage source 14, when the other terminal of capacitor Cf2 is connected to ground by switch means SPL2, to charge the second flying capacitor Cf2, and a low state where the second flying capacitor Cf2 is isolated from the first voltage source 14. A second discharge switch means SDCH2 is operable between a high state where the second flying capacitor Cf2 and the reservoir capacitor Crsvr are disconnected, and a low state wherein the second flying capacitor Cf2 and the reservoir capacitor Crsvr are connected, when the other terminal of capacitor Cf2 is connected to the pedestal voltage source 16, so that charge is transferred from the second flying capacitor Cf2 to the reservoir capacitor Crsvr.
The various switch means are controlled with control signals, shown with arrowheads in FIG. 1 and prefixed with the reference “B”. FIG. 1 shows for the sake of illustration one particular arrangement of the switches, where the switches are held in a position that occurs during a second charging period, as discussed later. The following references to FIG. 1 are intended to serve as a discussion of the various positions to which the illustrated switches are to be moved to, rather than meaning that each and every of the various positions are illustrated in FIG. 1. It is considered unnecessary to illustrate every possible configuration of the switches, as these would be too numerous. Rather, the various configurations will be well understood with reference to the diagram in FIG. 1 in conjunction with the explanation of the associated timing diagrams, as discussed later.
The sequencing of these switches must be carefully controlled to make sure that charge is correctly transferred within the circuit. The timing strategy of the various switches is illustrated in FIG. 2. It will be appreciated that the method of switching is cyclical and that any appropriate state of the switch means can be chosen as a nominal initial state. For the purposes of illustration, FIG. 2 illustrates an “initial” state wherein the charge previously gathered on the second flying capacitor Cf2 is being discharged to the reservoir capacitor Crsvr.
In this exemplary initial state, the first charge switch means SCH1 is held in a low state while the first discharge switch means SDCH1 is held in a high state, so that both switches are open. Similarly, a first pedestal switch means SPL1 is held in a low state, connected to the right so that the first flying capacitor Cf1 is connected to ground and isolated from the pedestal voltage source 16. Meanwhile, the second discharge switch means SDCH2 is held in a low state where the switch is closed, thus connecting the second flying capacitor Cf2 to the reservoir capacitor Crsvr; while the second pedestal switch means SPL2 is held in a high state, connected to the left hand side as shown in FIG. 1, such that the voltage provided by the first voltage source 14 is effectively raised by an amount equal to the voltage provided by the pedestal voltage source 16. Finally, the second charge switch SCH2 us held in a low state, open as shown in FIG. 1, such that the first voltage source 14 is isolated from the second flying capacitor Cf2. This situation is illustrated as time t=0, at the left side of the timing signals shown in FIG. 2, at which point the charge stored on the second flying capacitor Cf2 is being discharged to the reservoir capacitor Crsvr.
Starting from this state, the first charge switch means CH1 is raised to a high level so that, while the second flying capacitor Cf2 is still being discharged, the first voltage source 14 is connected to the first flying capacitor Cf1 and charge is gathered there. The time throughout the course of which the charging switch means is held in a high state is termed as a charging time or a charging period, and the control signal that achieves this is termed as a charge pulse, the width of which is understood to correlate to the time throughout which the signal holds the charge switch means in a high state. This terminology also applies to the second charge switch means SCH2, as described later.
After the first charge switch means SCH1 is switched back to a low state, the first pedestal switch PL1 is switched high, connecting the pedestal voltage source 16 to the first flying capacitor Cf1. Starting from this point in time, the first and second flying capacitors are connected, meaning that a small amount of charge may be transferred between them. After the first pedestal switch means 16 is switched high the first discharge switch means DCH1N is switched low (closed as shown in FIG. 1) so that the charge collected on the first flying capacitor Cf1 is discharged to the reservoir capacitor CRSVR, where once more the voltage provided by the first voltage source 14 is effectively raised by an amount equal to the voltage provided by the pedestal voltage source 16. The time throughout the course of which the discharge switch means is held in a low state is termed as a discharging time or a discharge period, and the control signal that achieves this is termed as a discharge pulse, the width of which is understood to correlate to the time throughout which the signal holds the discharge switch means in a low state. This terminology also applies to the second discharge switch means SDCH2 as described later.
After the first discharge switch means SDCH1 is switched low, the second discharge switch means SDCH2 is switched high (opening the switch as shown in FIG. 1) so that the reservoir capacitor Crsvr is isolated from the second flying capacitor Cf2, thus ending the discharge period for the second flying capacitor Cf2. After, and only after, the second discharge switch means SDCH2 has been put to high, the second pedestal switch means SPL2 is switched low (to the right as shown in FIG. 1) in order to isolate the second flying capacitor Cf2 from the pedestal voltage source 16 and from the first flying capacitor Cf1. Thus, once the switching has been completed, the second charge switch means SCH2 is put to high (closing the switch as shown in FIG. 1) such that the first voltage source 14 is connected to the second flying capacitor Cf2 to start the charge period for the second flying capacitor Cf2.
Once this charge period ends, the second pedestal switch means SPL2, second discharge switch means SDCH2, first discharge switch means SDCH1, first pedestal switch means SPL1 and first charge switch means CH1 operate sequentially in a similar fashion as described above to complete the cycle so that it is ready to start from the initial state once more.
The whole switching process is governed by the clock pulse CPCLK for the circuit, the falling edge of which corresponds to the falling edge of the first charge pulse and the rising edge of which corresponds to the falling edge of the second charge pulse. It is important that the switching is carried out in a strictly sequential fashion. The dependency of one switching operation on others is shown by the arrow heads in FIG. 2, where the switching at the head of the arrow must be performed after the switching at the foot of the arrow. These can in theory be carried out simultaneously, if gate delays are perfectly matched. This is however not possible in practice and it is therefore necessary to have a short delay between the pulse edge.
It will be seen from this timing sequence that the charge pulses (where CH1 and CH2 are high) are relatively narrow compared to the discharge pulses (where DCH1N and DCH2N are low). It can also be seen that there are overlap times, when a small amount of charge may be transferred between the flying capacitors, that is, there is a short period during which both the first pedestal switch SPL1 and the second pedestal switch SPL2 are high so that both are switched to the left and the two flying capacitors CF1 and CF2 are connected. The time period during which this connection occurs is illustrated by the dotted ovals 21 in FIG. 2. The efficiency with which charge is transferred to the load will be reduced if charge is allowed at any stage to flow between the first and second flying capacitors Cf1 and Cf2. This situation can not be eliminated with this switching scheme.
Charge pumps can be used in a wide variety of devices, and the scope of the invention is not limited to any particular device. However, for any given device, there is a requirement that a charge pump has to operate at a given frequency—this is represented by the clock pulse signal CPCLK in FIG. 2. The frequency at which a charge pump operates depends on how fast the flying capacitors can be charged and discharged. The rates of charge and discharge are illustrated schematically by the sloped shaded regions in FIG. 2. The rate of charge or discharge depends on the characteristics of the circuit (values of the various resistors and capacitors etc), the size of the reservoir capacitor, and the size of the load.
Circuit designers have been attempting to optimize circuit design to raise the frequency at which a charge pump can operate because of the advantages of physical size and the possibilities of integration that this provides.